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[브로드컴 2부] 빅테크 AI 칩-ASIC 설계 과정... 을 보면 핵심 기업 모두 등장 | tsmc 협력 XPU 개발한 브로드컴과 IP와 EDA 업체Synopsys Cadence

[브로드컴 2부] 빅테크 AI 칩-ASIC 설계 과정... 을 보면 핵심 기업 모두 등장 | tsmc 협력 XPU 개발한 브로드컴과 IP와 EDA 업체Synopsys Cadence

이번 영상에서는 브로드컴의 AI 칩 설계 과정을 통해 빅테크 기업들이 자체 AI 칩을 설계할 때, 어떻게 ASIC 개발을 진행하는지를 자세히 다룹니다....

IT

Youtube > 안될공학 - IT 테크 신기술

2 weeks ago

*This content was written based on sophisticated analysis of the entire script by Pentory AI.

Broadcom's Custom AI Chip Design: A New Value Chain and Growth Opportunities in the Big Tech Era

Summary

In response to the surging demand for AI chips, Broadcom is securing a dominant position in the design and manufacturing of custom AI chips through collaborations with Big Tech companies. This content details Broadcom's process of developing AI chips tailored to the needs of Big Tech firms like Google, Meta, and OpenAI, leveraging its diverse IP portfolio and automated design platform. Specifically, it highlights Broadcom's strategy of enabling high-performance, low-power AI chip production through advanced packaging technologies like the 3.5D XPU (eXpandable Processor Unit) and close collaboration with TSMC. The analysis also illuminates the resulting new value chain and the growth potential of related companies.

Key Points

  • Core of Custom AI Chip Design: Broadcom designs AI chips customized to client needs by assembling various IPs (particularly high-speed SerDes, memory controllers, and networking IPs) like Lego blocks. Automated design flows and AI-based optimization reduce design time and enhance efficiency.
  • 3.5D XPU and Advanced Packaging Technology: Broadcom is developing a 3.5D XPU integrating up to 12 stacks of HBM (High Bandwidth Memory) using 3.5D stacking technology. This is an optimized solution for high-performance computing (HPC) and AI workloads.
  • Joint Development with Big Tech Companies: Broadcom collaborates closely with Big Tech companies like Google, Meta, and OpenAI, developing custom AI chips within 7-9 months. This is crucial for accurately reflecting client requirements and achieving optimal performance.
  • Formation of a New Value Chain: The custom AI chip design and manufacturing process involves various companies beyond Broadcom, including TSMC (semiconductor manufacturing), Cadence and Synopsys (EDA tool providers), and AT (automated test equipment) companies, forming a new value chain.
  • Future Growth Potential: The increasing demand for AI chips indicates high growth potential for Broadcom and related companies. Companies in EDA tools, IP provision, and AT equipment are expected to be particularly noteworthy.

Details

This content analyzes the custom AI chip design and manufacturing ecosystem established by Broadcom in response to the rapidly growing demand for AI chips. AI chips require consideration of various factors beyond mere performance, including power efficiency, memory bandwidth, and inter-chip communication speed. Similar to Google's TPU (Tensor Processing Unit) series, Big Tech companies increasingly develop their own AI chips to optimize performance for their specific algorithms and workloads. Within this trend, Broadcom employs a strategy of meeting these demands using its self-developed IPs and advanced packaging technologies.

Broadcom's strength lies in its diverse IP portfolio. It possesses in-house high-speed SerDes (serializer/deserializer), memory controllers, PCIe (Peripheral Component Interconnect Express), Ethernet, and security-related IPs, allowing it to offer optimal configurations tailored to client needs. Furthermore, automated design flows and AI-based optimization technologies shorten design times and maximize power efficiency. This is a core competitive advantage, enabling the development of custom AI chips within a short timeframe of 7-9 months.

The 3.5D XPU exemplifies Broadcom's technological prowess. Through collaboration with TSMC, it utilizes cutting-edge 3nm processes and 3.5D stacking technology to integrate up to 12 stacks of HBM, securing immense memory bandwidth. This is essential for large-scale AI model training and inference. This chip design process isn't simply assembling components; it involves close collaboration with Big Tech's AI engineers to meticulously adjust parameters such as cache size, computing unit configuration, and power management.

The chip manufacturing process is broadly divided into logic design (RTL design using Verilog/VHDL) and physical design (routing, placement optimization) stages. EDA (Electronic Design Automation) tools from companies like Cadence and Synopsys are essential in this process, culminating in wafer fabrication through TSMC. Broadcom leverages its extensive experience and expertise throughout this process to provide clients with optimal solutions.

Implications

This content suggests that Broadcom's custom AI chip design strategy, through collaboration with Big Tech companies, is a crucial factor in forming a new value chain and stimulating industry growth. Broadcom's success stems not only from its inherent technological capabilities but also from close collaboration with clients and the integration of cutting-edge technologies. Future growth in the AI chip market will present even greater opportunities for companies like Broadcom with design and manufacturing capabilities. It is also expected to accelerate the development and growth of related industries such as EDA tools, IP provision, and AT equipment. Companies should refer to Broadcom's strategy to strengthen their own competitiveness and explore new market opportunities. Investment in automated design platforms and customer-centric solutions will be particularly crucial.

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